tsc693e ETC-unknow, tsc693e Datasheet - Page 23

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3.5.4. Power-Down Mode
This mode is entered by writing to the Power Down Register (see page 52) in the MEC,
which will cause the MEC bus arbiter to remove the bus ownership from the IU. The
entering of power-down mode must first permitted by programming the MEC Control
Register (see page 51).
In power-down mode the MEC asserts and maintains the BHOLD* and deasserts and
maintains the AOE*, COE*, and DOE* output signals. If an external interrupt is
asserted whilst being in power down mode the MEC deasserts the BHOLD* and asserts
the AOE*, COE*, and DOE* output signals. And thereafter ensures that all data at all
inputs to the IU/FPU are the same as it was before BHOLD* was asserted. The IU gets
back the bus ownership and the MEC leaves the power-down mode.
The MEC allows DMA accesses during power-down mode, in which DMA has
permanent access to the system, i.e. DMAGNT* is asserted immediately on DMA
request.
3.5.5. Error Halt Mode
Error Halt mode is entered under the following circumstances:
In Error Halt mode, the CPUHALT* and SYSERR* outputs of the MEC are asserted
(note that SYSERR* is also asserted if a masked error occurs even though Error Halt
mode is not entered in this case). All timers are halted and the UART operation is
stopped in this mode. The only way to exit Error Halt Mode is through Cold Reset by
asserting SYSRES*.
The MEC allows DMA accesses during error halt mode, in which DMA has permanent
access to the system, i.e. DMAGNT* is asserted immediately on DMA request.
Error Halt Mode can be induced by software by first setting the EWE bit in the Test
Control Register (see page 61) and then write an error to the Error and Reset Status
Register (see page 61). Note however that this also requires that the Reset/Halt bit for
the chosen error is set to halt in the MEC Control Register.
3.6. Wait-State and Timeout Generator
It is possible to control the wait state generation by programming a Waitstate
Configuration Register (see page 55) in the MEC. The maximum programmable
number of wait-states is applied as default at reset.
MATRA MHS
Rev. D (10 Apr. 97)
A hardware parity error, EDAC uncorrectable error or a comparison error (see
paragraph 3.17.) has occurred.
The IU enters error mode (by asserting the ERROR* output)
TSC693E
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