tsc693e ETC-unknow, tsc693e Datasheet - Page 3

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

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APPENDIX 1 - TIMING DIAGRAMS
MATRA MHS
Rev. D (10 Apr. 97)
MEMORY CONTROLLER SIGNAL DESCRIPTIONS ......................... 63
ELECTRICAL AND MECHANICAL SPECIFICATION........................ 80
Memory Redundancy .............................................................................. 32
Synchronous Traps .................................................................................. 32
Interrupts (Asynchronous Traps)............................................................. 33
General Purpose and Real Time Clock Timers ....................................... 36
Watch Dog............................................................................................... 38
UART ...................................................................................................... 40
Parity Checking ....................................................................................... 41
Error Handler........................................................................................... 42
System Availability ................................................................................. 47
Test mode and Test Access Port.............................................................. 47
System Clock........................................................................................... 48
MEC Registers ........................................................................................ 49
Memory Controller Signal Summary ...................................................... 63
MEC Detailed Signal Descriptions ......................................................... 65
Maximum Rating and DC Characteristics .............................................. 80
Package Description ................................................................................ 81
Fault Injection ....................................................................................... 31
Memory and I/O Parity ......................................................................... 31
EDAC Test............................................................................................ 47
Parity Test ............................................................................................. 47
Interrupt Test......................................................................................... 47
Error Test .............................................................................................. 48
Test Access Port (TAP) ........................................................................ 48
Register Address Map........................................................................... 49
Register Configuration and Bit Allocation ........................................... 50
IU/FPU Interface Signals ...................................................................... 65
Memory System Interface Signals ........................................................ 71
Interrupt and Control Signals................................................................ 75
Test Access Port Signals....................................................................... 77
UART Interface..................................................................................... 78
Power and Clock Signals ...................................................................... 79
Maximum Ratings................................................................................. 80
Operating Range ................................................................................... 80
DC Characteristics over the Operating Range ...................................... 80
Capacitance Ratings.............................................................................. 81
Pin Assignments.................................................................................... 81
Package Diagram .................................................................................. 82
TSC693E
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