tsc693e ETC-unknow, tsc693e Datasheet - Page 48

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

Interrupt test mode is enabled in the Test Control Register (see page 61).
3.19.4. Error Test
The MEC error detection and handling allows fault injection for test purpose. By
enabling Error test mode in TCR (EWE=1), an error could be simulated by writing to
the Error and Reset Status Register, bits 5-0.
3.19.5. Test Access Port (TAP)
The MEC includes a Test Access Port (TAP) interface (IEEE standard 1149.1) for
debugging and test purposes. The TAP does however not implement any scan function
in the present version of the MEC, and only implements the Bypass register.
The timing of the TAP signals is according to IEEE 1149.1. This means that TDI and
TMS are sampled by the ERC32 devices on the rising edge of TCK, and that TDO is
driven on the falling edge .
Figure 12 - removed
3.20. System Clock
The MEC provides a system clock signal (SYSCLK) with a nominal 50 % duty cycle for
the IU/FPU and the rest of the system.
The system clock is obtained by dividing an external clock signal (CLK2) by two.
Please note that the MEC itself uses both SYSCLK and CLK2 directly. Some MEC
output signals are clocked by the CLK2 negative edge which means that the CLK2 duty
cycle has a direct impact on the system performance.
When interfacing peripherals (I/O interface, DMA interface etc.) it is highly
recommended that only SYSCLK rising edge is used as reference as far as possible.
CLK2 should be used as input to the MEC only.
MATRA MHS
Rev. D (10 Apr. 97)
-
When the interrupt is acknowledged, the MEC will automatically clear the
corresponding bit in the IFR if this bit is set, otherwise it will clear the
corresponding bit in the IPR. In this way no external interrupts are lost.
TSC693E
48