tsc693e ETC-unknow, tsc693e Datasheet - Page 33

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3.12. Interrupts (Asynchronous Traps)
The MEC handles 15 different events corresponding to asynchronous traps.
The MEC allocates each specific interrupt to an interrupt level. The interrupt allocation
is in accordance with the scheme in Table 5 (page 35).
The following interrupts, representing asynchronous traps, asserts the Interrupt Request
Level (IRL) inputs of the processor:
MATRA MHS
Rev. D (10 Apr. 97)
Parity error on control bus
This occurs if the MEC detects a parity error on the external control bus.
Parity error on the data bus
This trap occurs if the MEC detects a parity error on the external data bus.
Parity error on address bus
This trap occurs if the MEC detects a parity error on the external address bus.
Access to protected area
This trap occurs if any addressing device performs an access which does not
match the memory protection scheme.
Access to unimplemented area
This trap occurs if any addressing device performs an access with invalid address
to an unimplemented area.
MEC register access violation
This trap occurs if an illegal access is attempted to an internal MEC register.
Uncorrectable error in memory
The trap occurs if the EDAC detects a non-correctable error.
Bus time-out
This trap occurs if the ready generation times out i.e. if, during a BUSRDY*
controlled access, BUSRDY* is not asserted within 256 clock cycles.
System bus error
This trap occurs if the Bus error (BUSERR*) input is asserted.
Watch Dog time-out
This interrupt occurs if the watchdog timer times out.
DMA time-out
This interrupt occurs if the DMA session exceeds permitted time.
TSC693E
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