tsc693e ETC-unknow, tsc693e Datasheet - Page 15

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
3.2.4. Exchange Memory
The MEC supports a dedicated exchange memory area that can be used for system bus
interchange of data.
The following sizes of the exchange memory are allowed: 4 Kbytes, 8 Kbytes,
16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes, 256 Kbytes, and 512 Kbytes. Selection of
exchange memory size is done by programming the Memory Configuration Register
(see page 52). The default value of the exchange memory size after system reset is the
minimum size, 4 Kbytes. The MEC provides one exchange memory chip select output.
Only word access is allowed in the exchange memory area. Any attempt to access byte
or halfword data in the exchange memory will cause a memory exception.
In case the exchange memory includes EDAC check bits and parity bits, these protection
bits will be treated in the same manner as for the main memory. If the exchange memory
does not include any check bits, the MEC will generate the parity to the IU. The default
is that no EDAC or parity is implemented in the exchange memory. If the exchange
memory implements check bits, this must be defined in the Memory Configuration
Register in the MEC during start up and initialization.
The MEC is designed to allow implementation of the exchange memory with a
DPRAM. The BUSY signal from the DPRAM can then be connected to the BUSRDY*
signal of the MEC. The MEC waits one cycle at the start of the access for the assertion
of the BUSRDY* signal. If the BUSRDY* signal is asserted in the beginning of the
second cycle, the normal data wait-state controlled access continues. If the BUSRDY*
signal is deasserted during the wait-states, the MEC will delay the access until the
BUSRDY* signal has been asserted and then continue with the normal data wait-state
controlled access. If a cycle is prolonged to more than 256 clock cycles, the Bus
Timeout function will signal a system bus error.
The minimum length of an exchange memory access is three clock cycles.
3.2.5. I/O
Four address decoded I/O select outputs are provided in the MEC.
The minimum length of an I/O access for each I/O select is programmable in the MEC.
The BUSRDY* signal is used to prolong I/O access for devices with variable access
time. The BUSERR* signal is used to signal to the MEC that a bus error has occurred.
Table 2 gives the encoding for the system bus transaction response signals. The
transactions that signal a system bus error, set the corresponding bit in the System Fault
Status Register (SFSR) of the MEC, which then responds by asserting Error to the
interrupt logic. These bits describe system bus error cases, in addition the bus timeout is
set if the internal bus time out timer causes abortion.
MATRA MHS
Rev. D (10 Apr. 97)
15