tsc693e ETC-unknow, tsc693e Datasheet - Page 18

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3.2.6. MEC Memory Map
The MEC memory map is shown in Table 3.
1) Neither access protection nor chip select generation is performed by the MEC for the
extended areas. Note that these areas are only controlled by the BUSRDY* signal.
In the I/O areas and in the Extended areas one waitstate is always inserted, since the
MEC has to wait for the BUSRDY* signal. In the Exchange Memory area two
waitstates are always inserted to wait for the BUSRDY* signal. In the I/O areas and in
the Extended areas the BUSRDY* signal works as a ready signal to tell the accessing
unit that data is ready. In the Exchange Memory area the BUSRDY* signal works as a
busy signal to tell the accessing unit that the access can not yet start.
MATRA MHS
Rev. D (10 Apr. 97)
Address
(hexadecimal)
0x00000000
0x01000000
0x01F00000
0x01F80000
0x02000000
0x04000000
0x10000000
0x11000000
0x12000000
0x13000000
0x14000000
0x80000000
Table 3 - MEC Memory map
Memory contents
Boot PROM
Extended PROM area
BUSRDY* controlled
Exchange memory
BUSRDY* controlled
MEC Registers
RAM Memory
(8 blocks)
Extended RAM area
BUSRDY* controlled
I/O area 0
I/O area 1
I/O area 2
I/O area 3
Extended I/O area
BUSRDY* controlled
Extended general area
BUSRDY* controlled
1)
1)
1)
1)
Size (Bytes)
128k - 16M
15M
4k - 512k
512k (136 used)
8 * 32k - 8 * 4M
192M
0 - 16M
0 - 16M
0 - 16M
0 - 16M
1728M
2G
Data size and parity
options
* 8-bit mode
8 to 32 bit conversion
No parity
Only byte write
* 40-bit mode
Parity+EDAC mandatory
Only word write
The same settings as for
Boot PROM
Parity/EDAC options
Only word accesses
Parity only
Word write and Word/
Hword/ Byte read
Parity/EDAC options
All data sizes allowed
The same settings as for
RAM Memory
Parity option
All data sizes allowed
As above
As above
As above
The same settings as for
I/O area 3
No parity/EDAC
All data sizes allowed
TSC693E
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