tsc693e ETC-unknow, tsc693e Datasheet - Page 75

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
4.2.3. Interrupt and Control Signals
IRL[3:0] - Interrupt Request Level (output)
The state of these pins defines the Interrupt Request Level (IRL). IRL[3:0] = 0000
indicates that no external interrupts are pending and is the normal state of the IRL pins.
IRL[3:0] = 1111 signifies a nonmaskable interrupt. All other interrupt levels are
maskable by the Processor Interrupt Level (PIL) field of the Processor State Register
(PSR). External interrupts are latched and prioritized by the MEC before they are passed
to the IU.
INTACK - Interrupt Acknowledge (input)
INTACK is asserted by the IU when an external interrupt is taken, not when it is
sampled and latched. The MEC will clear the corresponding pending interrupt when
INTACK is asserted.
EXTINT[4:0] - External Interrupt (input)
The five external interrupt inputs are programmable to be level or edge sensitive, and
active high (rising) or active low (falling).
EXTINTACK - External Interrupt Acknowledge (output)
EXTINTACK is for giving acknowledge to an interrupting unit which requires such a
signal. It is programmable to which of the five external interrupt input it is associated. It
is issued as soon as the IU has recognized the interrupt by asserting the INTACK signal.
SYSRESET* - System Reset (input)
Assertion of this pin will reset the MEC. Following this the MEC will then assert
RESET* for a minimum of sixteen clock cycles. SYSRESET* must be asserted for a
minimum of four clock cycles.
RESET* - Reset (output)
RESET* will be asserted when the IU and the FPU is to be synchronously reset. This
occurs when either SYSRESET* is asserted or the MEC initiate a reset due to an error
or a programming command.
MATRA MHS
Rev. D (10 Apr. 97)
75