tsc693e ETC-unknow, tsc693e Datasheet - Page 72

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
ROMCS* - PROM Chip Select (output)
This output is asserted whenever there is an access to the PROM. It can be connected
directly to the PROM chip select pins.
MEMCS*[9:0] - Memory Chip Select (output)
MEMCS*[9:0] is asserted during an access to the main memory. MEMCS*[9:8] are
redundant signals, used to substitute any of the nominal memory banks when memory
connected to any of MEMCS*[7:0] malfunctions.
OE*[1:0] - Output Enable (output)
OE*[1:0] are asserted during read accesses to the main memory and is used to control
memory devices with output enable features. Two signals are provided in order to avoid
an external buffer, since a single OE* signal would be too heavily loaded in typical
system.
MEMWR1*[1:0] - Memory Write (output)
MEMWR1* is asserted during write access to RAM, extended RAM, boot PROM
extended boot PROM. It is intended to be used as write strobe to the memory devices. If
latching buffers are used for the data bus, this signal can be used as a strobe to latch the
data and the MEMWR2* signal can be used to write the data into the main memory.
Two signals are provided in order to avoid an external buffer, since a single signal
would be too heavily loaded in typical system.
MEMWR2*[1:0] - Check Bit Write (output)
MEMWR2* is asserted during write access to RAM, extended RAM, boot PROM
extended boot PROM and exchange memory. It is intended to be used as write strobe to
check bit memory devices, if implemented. If latching buffers are used for the data bus,
this signal can be used to write both the check bits into the check bit memory and the
data bits into the main memory. Two signals are provided in order to avoid an external
buffer, since a single signal would be too heavily loaded in typical system.
RAMBEN* - RAM Buffer Enable (output)
RAMBEN* is asserted during memory accesses to RAM. It is intended to be used as
buffer enable for data and check bit buffers in the RAM.
MATRA MHS
Rev. D (10 Apr. 97)
72