tsc693e ETC-unknow, tsc693e Datasheet - Page 42

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3.17. Error Handler
The MEC has one error output signal (SYSERR*) which indicates that an unmasked
error has occurred. Any error signaled on the error inputs from the IU and the FPU is
latched and reflected in the Error and Reset Status Register (see page 61).
It is possible to program an error mask in the MEC Control Register for each type of
error in order to determine whether the specific error shall lead to the MEC ignoring the
error or asserting a processor halt or processor reset. It is possible to choose either a
processor halt or processor reset by programming the MEC Control Register (see page
51). As default, an error leads to a processor halt.
All unmasked errors, asserts the SYSERR* pin and this pin is asserted until all the
unmasked error bits in the Error and Reset Status Register (see page 61) are cleared.
In Figure 8 a schematic view of the error handler is shown.
Figure 8 - Error Handler Schematic
A MEC hardware error occurs, if a parity error is detected on the internal registers. A
detected MEC hardware error will cause the MEC to assert the MECHWERR* and
SYSERR* signals. The memory exception output (MEXC*) is not asserted in this case.
MATRA MHS
Rev. D (10 Apr. 97)
Errors
ERSR
IMR
MCR Error Mask
&
&
>1
MCR
Reset
Halt
SYSERR*
TSC693E
Masked Hardware Error
Interrupt Level 1
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