tsc693e ETC-unknow, tsc693e Datasheet - Page 85

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

MATRA MHS
Rev. D (10 Apr. 97)
Name
t1
t2
t3
t4
t5
t6
t7
t8
t9 *)
t10*)
t11
t12 *)
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27 **)
t28
t29
t30
t31
t32
t35
t36
t37
t38
t39
t40
t42
t43
t44
t45
t46
t47
t48
t49
t50
t53
t54
Min
56
0,45*t3
28
15
4
15
4
1
1
2
2
8
4
8
4
35
4
15
4
15
8
4
8
4
8
4
15
4
20
Max
0,55*t3
15
20
15
8
35
35
35
35
30
20
35
15
15
15
15
15
20
20
20
20
Comment
SYSCLK period
CLK2, high and low pulse width
CLK2 period
Address Input Setup Time
Address Input Hold Time
ASI(7:0), SIZE(1:0), RD, WRT, WE*, LOCK, LDSTO, DXFER Input Setup
Time
ASI(7:0), SIZE(1:0), RD, WRT, WE*, LOCK, LDSTO, DXFER Input Hold
Time
ALE* Output Delay
Address Valid to MEC Internal Chip Select Delay
MEMCS*(9:0), ROMCS*, EXMCS* Maximum Clock to
Output Delay
MEMCS*(9:0), ROMCS*, EXMCS* Minimum Clock to
Output Delay
MEMCS*(9:0), ROMCS*, EXMCS* Output Latch
Propagation Delay
MEMBEN*, RAMBEN*, ROMBEN* Output Delay
DDIR Output Delay
MEMWR1*, MEMWR2*, IOWR* Output Delay
OE* Output Delay
Boot PROM Address (BA) Output Delay
IOSEL*(3:0) Clock to Output Delay
Data Setup Time During Store
Data Hold Time During Store
MEC Data and DPARIO Maximum Output Delay
MEC Data and DPARIO Valid to High-Z Delay
CB* Output Maximum Delay
CB* Output Valid to High-Z Delay
MEXC* Output Delay
MHOLD*, BHOLD* Output Delay
AOE*, COE*, DOE*, TOE* Output Delay
INTACK Input Setup Time
INTACK Input Hold Time
SYSRESET*, SYSHALT* Input Setup
SYSRESET*, SYSHALT* Input Hold
RESET*, CPUHALT* Output Delay
INULL Input Setup
INULL Input Hold
MDS/DRDY* Output Delay
BUSRDY*, BUSERR* Input Setup
BUSRDY*, BUSERR* Input Hold
DMAREQ* Input Setup Time
DMAGNT* Output Delay
IRL(3:0), EXTINTACK Output Delay
EXTINT(4:0) Input Setup
EXTINT(4:0) Input Hold
IUERR*, IUHWERR, IUCMPERR*, FPUHWERR*, FPUCMPERR* Input
Setup
IUERR*, IUHWERR, IUCMPERR*, FPUHWERR*, FPUCMPERR* Input
Hold
SYSERR*, SYSAV, MECHWERR* Output Delay
NOPAR, ROMWRT*, PROM8* Input Setup Time
NOPAR, ROMWRT*, PROM8* Input Hold Time
APAR, ASPAR, IMPAR Input Setup Time
APAR, ASPAR, IMPAR Input Hold Time
TSC693E
Reference Edge
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK-
Address Valid
SYSCLK+
SYSCLK+
CLK2+ (lo->hi),
CLK2- (hi->lo)
CLK2+
CLK2-
CLK2+ (lo->hi),
CLK2- (hi->lo)
SYSCLK+
SYSCLK- (lo->hi),
SYSCLK+ (hi->lo)
SYSCLK-
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK-
SYSCLK-
SYSCLK+
SYSCLK+
SYSCLK+
SYSCLK+
SYSRESET-
SYSRESET+
SYSCLK+
SYSCLK+
SYSCLK-
3