h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 11

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

5.4
5.5
5.6
5.7
Section 6 PC Break Controller (PBC) .................................................................93
6.1
6.2
6.3
6.4
5.3.2
5.3.3
5.3.4
Interrupt Sources.................................................................................................................. 78
5.4.1
5.4.2
Interrupt Exception Handling Vector Table......................................................................... 79
Interrupt Control Modes and Interrupt Operation ................................................................ 83
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Usage Notes ......................................................................................................................... 91
5.7.1
5.7.2
5.7.3
5.7.4
Features................................................................................................................................ 93
Register Descriptions ........................................................................................................... 94
6.2.1
6.2.2
6.2.3
6.2.4
Operation ............................................................................................................................. 96
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Usage Notes ....................................................................................................................... 100
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
IRQ Enable Register (IER) ..................................................................................... 74
IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 75
IRQ Status Register (ISR)....................................................................................... 77
External Interrupts .................................................................................................. 78
Internal Interrupts ................................................................................................... 79
Interrupt Control Mode 0 ........................................................................................ 83
Interrupt Control Mode 2 ........................................................................................ 85
Interrupt Exception Handling Sequence ................................................................. 87
Interrupt Response Times ....................................................................................... 89
DTC Activation by Interrupt................................................................................... 90
Conflict between Interrupt Generation and Disabling ............................................ 91
Instructions that Disable Interrupts ......................................................................... 92
When Interrupts Are Disabled ................................................................................ 92
Interrupts during Execution of EEPMOV Instruction............................................. 92
Break Address Register A (BARA) ........................................................................ 94
Break Address Register B (BARB) ........................................................................ 95
Break Control Register A (BCRA) ......................................................................... 95
Break Control Register B (BCRB).......................................................................... 96
PC Break Interrupt Due to Instruction Fetch .......................................................... 96
PC Break Interrupt Due to Data Access.................................................................. 97
PC Break Operation at Consecutive Data Transfer................................................. 97
Operation in Transitions to Power-Down Modes ................................................... 97
When Instruction Execution Is Delayed by One State............................................ 99
Module Stop Mode Setting ................................................................................... 100
PC Break Interrupts .............................................................................................. 100
CMFA and CMFB ................................................................................................ 100
PC Break Interrupt when DTC Is Bus Master ...................................................... 100
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,
TRAPA, RTE, or RTS Instruction ........................................................................ 100
I Bit Set by LDC, ANDC, ORC, or XORC Instruction ........................................ 100
Rev. 2.00 Dec. 05, 2005 Page xi of xxxviii