h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 581

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE800
6. Before branching to the programming control program, the chip terminates transfer operations
7. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
8. All interrupts are disabled during programming or erasing of the flash memory.
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 19.5.
to H'FFEFBF is the area to which the programming control program is transferred from the
host. The boot program area cannot be used until the execution state in boot mode switches to
the programming control program.
by SCI_1 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TxD pin is high. The contents of the CPU general
registers are undefined immediately after branching to the programming control program.
These registers must be initialized at the beginning of the programming control program, as the
stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
the FWE pin and mode pins, and executing reset release. Boot mode is also cleared when a
WDT overflow occurs.
Rev. 2.00 Dec. 05, 2005 Page 543 of 724
REJ09B0200-0200
Section 19 ROM