h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 31

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 17 LCD Controller/Driver
Figure 17.1 Block Diagram of LCD Controller/Driver .............................................................. 510
Figure 17.2 Handling of LCD Drive Power Supply when Using 1/2 Duty ................................ 518
Figure 17.3 LCD RAM Map (1/4 Duty)..................................................................................... 520
Figure 17.4 LCD RAM Map (1/3 Duty)..................................................................................... 521
Figure 17.5 LCD RAM Map (1/2 Duty)..................................................................................... 521
Figure 17.6 LCD RAM Map (Static Mode)................................................................................ 522
Figure 17.7 Output Waveforms for Each Duty Cycle (A Waveform) ........................................ 523
Figure 17.8 Output Waveforms for Each Duty Cycle (B Waveform) ........................................ 524
Figure 17.9 Connection of External Split-Resistance ................................................................. 526
Section 19 ROM
Figure 19.1 Block Diagram of Flash Memory............................................................................ 530
Figure 19.2 Flash Memory State Transitions.............................................................................. 531
Figure 19.3 Boot Mode............................................................................................................... 532
Figure 19.4 User Program Mode (Example)............................................................................... 533
Figure 19.5 Flash Memory Block Configuration........................................................................ 535
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 545
Figure 19.7 Flowchart for Flash Memory Emulation in RAM ................................................... 546
Figure 19.8 Example of RAM Overlap Operation...................................................................... 548
Figure 19.9 Program/Program-Verify Flowchart........................................................................ 550
Figure 19.10 Erase/Erase-Verify Flowchart ............................................................................... 552
Section 20 Clock Pulse Generator
Figure 20.1 Block Diagram of Clock Pulse Generator ............................................................... 559
Figure 20.2 Connection of Crystal Resonator (Example)........................................................... 562
Figure 20.3 Crystal Resonator Equivalent Circuit ...................................................................... 562
Figure 20.4 External Clock Input (Examples) ............................................................................ 563
Figure 20.5 External Clock Input Timing................................................................................... 564
Figure 20.6 Connection Example of 32.768-kHz Crystal Resonator.......................................... 566
Figure 20.7 Equivalent Circuit for 32.768-kHz Crystal Resonator............................................. 566
Figure 20.8 Pin Handling when Subclock is not Used ............................................................... 567
Figure 20.9 Note on Board Design of Oscillator Circuit ............................................................ 568
Figure 20.10 External Circuitry Recommended for PLL Circuit................................................ 568
Section 21 Power-Down Modes
Figure 21.1 Mode Transition Diagram ....................................................................................... 571
Figure 21.2 Medium-Speed Mode Transition and Clearance Timing ........................................ 581
Figure 21.3 Software Standby Mode Application Example ....................................................... 583
Figure 21.4 Hardware Standby Mode Timing ............................................................................ 584
Rev. 2.00 Dec. 05, 2005 Page xxxi of xxxviii