h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 592

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h8s-2649

Manufacturer Part Number
h8s-2649
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 19 ROM
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase
mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be
re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition
can be made to verify mode. Error protection can be cleared only by a reset or in hardware
standby.
19.10
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot
mode*
1. Interrupt during programming or erasing might cause a violation of the programming or
2. In the interrupt exception handling sequence during programming or erasing, the vector would
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming
19.11
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as for a discrete flash memory. Use a PROM programmer which supports the
Renesas 256-kbyte flash memory on-chip microcomputer device type (FZTAT256V5A).
Rev. 2.00 Dec. 05, 2005 Page 554 of 724
REJ09B0200-0200
erasing algorithm, with the result that normal operation could not be assured.
not be read correctly*
normal boot mode sequence.
1
, to give priority to the program or erase operation. There are three reasons for this:
2. The vector may not be read correctly in this case for the following two reasons:
Interrupt Handling when Programming/Erasing Flash Memory
Programmer Mode
control program has completed programming.
• If flash memory is read while being programmed or erased (while the P or E bit is set
• If the interrupt entry in the vector table has not been programmed yet, interrupt
in FLMCR1), correct read data will not be obtained (undetermined values will be
returned).
exception handling will not be executed correctly.
2
, possibly resulting in CPU runaway.

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