h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 197
h8s-2649
Manufacturer Part Number
h8s-2649
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2649.pdf
(766 pages)
- Current page: 197 of 766
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8.7
8.7.1
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the
5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in
6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is held
= 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where data will be received in
DAR, and 128 (H′0080) in CRA. CRB can be set to any value.
reception complete (RXI) interrupt. Since the generation of a receive error during the SCI
reception operation will disable subsequent reception, the CPU should be enabled to accept
receive error interrupts.
SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is
transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented.
The RDRF flag is automatically cleared to 0.
at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The
interrupt handling routine will perform wrap-up processing.
Examples of Use of the DTC
Normal Mode
Rev. 2.00 Dec. 05, 2005 Page 159 of 724
Section 8 Data Transfer Controller (DTC)
REJ09B0200-0200
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