h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 121

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

5.6
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
5.6.1
In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit in CCR
in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests
3. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
Interrupt
Control Mode
0
2
interrupt request is sent to the interrupt controller.
are held pending. If the I bit is cleared, an interrupt request is accepted.
priority according to the interrupt priority levels is selected and other interrupt requests are
held pending.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
Interrupt Control Modes and Interrupt Operation
Interrupt Control Mode 0
Interrupt Control Modes
Priority Setting
Registers
Default
IPR
Interrupt
Mask Bits Description
I
I2 to I0
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources, except for NMI, are masked
by the I bit.
8 priority levels other than NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
Rev. 2.00 Dec. 05, 2005 Page 83 of 724
Section 5 Interrupt Controller
REJ09B0200-0200