h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 299

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

10.3.4
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The TPU has six TIER registers, one for each channel.
Bit
7
6
5
4
3
Bit Name
TTGE

TCIEU
TCIEV
TGIED
Timer Interrupt Enable Register (TIER)
Initial
value
0
1
0
0
0
R/W
R/W

R/W
R/W
R/W
A/D Conversion Start Request Enable
Underflow Interrupt Enable
Overflow Interrupt Enable
TGR Interrupt Enable D
Description
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This bit is always read as 1 and cannot be modified.
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always read
as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
Rev. 2.00 Dec. 05, 2005 Page 261 of 724
Section 10 16-Bit Timer Pulse Unit (TPU)
REJ09B0200-0200