h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 16

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

10.4 Operation ........................................................................................................................... 268
10.5 Interrupt Sources................................................................................................................ 293
10.6 DTC Activation.................................................................................................................. 295
10.7 A/D Converter Activation.................................................................................................. 295
10.8 Operation Timing............................................................................................................... 296
10.9 Usage Notes ....................................................................................................................... 304
Rev. 2.00 Dec. 05, 2005 Page xvi of xxxviii
10.3.1 Timer Control Register (TCR).............................................................................. 237
10.3.2 Timer Mode Register (TMDR)............................................................................. 242
10.3.3 Timer I/O Control Register (TIOR)...................................................................... 244
10.3.4 Timer Interrupt Enable Register (TIER)............................................................... 261
10.3.5 Timer Status Register (TSR)................................................................................. 263
10.3.6 Timer Counter (TCNT)......................................................................................... 266
10.3.7 Timer General Register (TGR) ............................................................................. 266
10.3.8 Timer Start Register (TSTR) ................................................................................ 266
10.3.9 Timer Synchro Register (TSYR) .......................................................................... 267
10.4.1 Basic Functions..................................................................................................... 268
10.4.2 Synchronous Operation......................................................................................... 274
10.4.3 Buffer Operation................................................................................................... 276
10.4.4 Cascaded Operation .............................................................................................. 280
10.4.5 PWM Modes......................................................................................................... 282
10.4.6 Phase Counting Mode........................................................................................... 287
10.8.1 Input/Output Timing............................................................................................. 296
10.8.2 Interrupt Signal Timing ........................................................................................ 300
10.9.1 Module Stop Mode Setting ................................................................................... 304
10.9.2 Input Clock Restrictions ....................................................................................... 304
10.9.3 Caution on Period Setting ..................................................................................... 305
10.9.4 Conflict between TCNT Write and Clear Operations .......................................... 305
10.9.5 Conflict between TCNT Write and Increment Operations ................................... 306
10.9.6 Conflict between TGR Write and Compare Match............................................... 307
10.9.7 Conflict between Buffer Register Write and Compare Match.............................. 308
10.9.8 Conflict between TGR Read and Input Capture ................................................... 309
10.9.9 Conflict between TGR Write and Input Capture .................................................. 310
10.9.10 Conflict between Buffer Register Write and Input Capture.................................. 311
10.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................. 312
10.9.12 Conflict between TCNT Write and Overflow/Underflow .................................... 313
10.9.13 Multiplexing of I/O Pins ....................................................................................... 313
10.9.14 Interrupts in Module Stop Mode........................................................................... 313