h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 172

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 7 Bus Controller (BSC)
7.9
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are two bus masters—the CPU and DTC—that perform read/write operations when they
have the bus mastership. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes the bus mastership and begins
its operation.
7.9.1
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master. If there are bus requests from more than one
bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a
bus master receives the bus request acknowledge signal, it takes the bus mastership until that
signal is canceled.
The order of priority of the bus masterships is as follows:
7.9.2
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
• With bit manipulation instructions such as BSET and BCRL, the sequence of operations is:
• If the CPU is in sleep mode, the bus is transferred immediately.
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discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
(High) DTC > CPU (Low)
Bus Arbitration
Operation
Bus Transfer Timing