h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 382

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 12 Watchdog Timer (WDT)
12.3
12.3.1
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
When the WDT is used as a watchdog timer, and if TCNT overflows without being rewritten
because of a system malfunction or other error, a WDTOVF signal is output when using the
WDT_0.
In watchdog timer mode, the WDT can internally reset this LSI with a WDTOVF signal.
When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal
for this LSI is issued at the same time as a WDTOVF signal. In this case, select power-on reset by
setting the RSTS bit in RSTCSR to 0.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when the RSTE bit = 1 in RSTCSR, and for 130
states when the RSTE bit = 0.
The internal reset signal is output for 518 states. This is illustrated in figure 12.3 (a).
When the TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If the
RSTE bit in RSTCSR has been set to 1, an internal reset signal for the entire LSI is generated at
TCNT overflow.
In the case of the WDT_1, the chip is reset, or an NMI interrupt request is generated, for 516
system clock periods (516 φ) (515 or 516 states when the clock source is φSUB (PSS = 1)). This is
illustrated in figure 12.3 (b).
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
both treated as having the same vector. So, avoid handling an NMI interrupt request from the
watchdog timer and an interrupt request from the NMI pin at the same time.
Rev. 2.00 Dec. 05, 2005 Page 344 of 724
REJ09B0200-0200
Operation
Watchdog Timer Mode