h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 381

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

12.2.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
and not by the WDT internal reset signal caused by overflows.
Note:
Bit
7
6
5
4 to 0
*
Bit Name
WOVF
RSTE
RSTS
—
Reset Control/Status Register (RSTCSR)
Only 0 can be written, for flag clearing.
0
0
Initial
Value
0
All 1
R/W
R/(W)* Watchdog Overflow Flag
R/W
R/W
—
Reset Enable
Reset Select
Description
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode, and
only 0 can be written.
[Setting condition]
•
[Clearing condition]
•
Specifies whether or not a reset signal is generated in
the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT overflows
1: Reset signal is generated if TCNT overflows
Selects the type of internal reset generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset
1: Setting prohibited
Reserved
These bits are always read as 1 and cannot be
modified.
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
Rev. 2.00 Dec. 05, 2005 Page 343 of 724
Section 12 Watchdog Timer (WDT)
REJ09B0200-0200