h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 97

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

4.1
As shown in table 4.1, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority
High
Low
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in program
Exception Handling Types and Priority
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Type
Trace*
Direct transition
Interrupt
Reset
Trap instruction *
Exception Types and Priority
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Section 4 Exception Handling
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in EXR is set to 1.
Starts when a direction transition occurs as the result of
SLEEP instruction execution.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.*
Started by execution of a trap instruction (TRAPA).
Rev. 2.00 Dec. 05, 2005 Page 59 of 724
Section 4 Exception Handling
REJ09B0200-0200
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