h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 416

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 Serial Communication Interface (SCI)
13.4.5
Figure 13.6 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark
Figure 13.7 shows a sample flowchart for transmission in asynchronous mode.
Rev. 2.00 Dec. 05, 2005 Page 378 of 724
REJ09B0200-0200
data has been written to TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI)
is generated. Continuous transmission is possible because the TXI interrupt routine writes next
transmit data to TDR before transmission of the current transmit data has been completed.
multiprocessor bit (may be omitted depending on the format), and stop bit.
serial transmission of the next frame is started.
state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
TXI interrupt
request generated
TDRE
TEND
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
Data Transmission (Asynchronous Mode)
1
Start
bit
0
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine
D0
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
1 frame
Data
D7
Parity
bit
0/1
TXI interrupt
request generated
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
TEI interrupt
request generated
0/1
Stop
bit
1
Idle state
(mark state)
1