h8s-2649 Renesas Electronics Corporation., h8s-2649 Datasheet - Page 280

• Manufacturer Part Number: h8s-2649
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings
should be changed only when TCNT operation is stopped.
Rev. 2.00 Dec. 05, 2005 Page 242 of 724
REJ09B0200-0200
Bit
7, 6
5
4
3
2
1
0
Bit Name

BFB
BFA
MD3
MD2
MD1
MD0
Timer Mode Register (TMDR)
Initial
value
All 1
0
0
0
0
0
0
R/W

R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
Modes 0 to 3
These bits are used to set the timer operating mode.
MD3 is a reserved bit. In a write, it should always be
written with 0. See table 10.11 for details.