HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 224

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
6.3.8
DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Bit
15
14
13
Rev.7.00 Mar. 18, 2009 page 156 of 1136
REJ09B0109-0700
Bit Name
OEE
RAST
—
DRAM Control Register (DRAMCR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
OE Output Enable
The OE signal used when EDO page mode DRAM
is connected can be output from the (OE) pin. The
OE signal is common to all areas designated as
DRAM space.
When the synchronous DRAM is connected, the
CKE signal can be output from the (OE) pin. The
CKE signal is common to the continuous
synchronous DRAM space.
0: OE/CKE signal output disabled
1: OE/CKE signal output enabled
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS signal
is asserted from the start of the T
edge of φ) or from the falling edge of φ.
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in T
1: RAS is asserted from start of T
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
(OE)/(CKE) pin can be used as I/O port
r
r
cycle (rising
cycle
r
cycle