HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 510

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Data Transfer Controller (DTC)
9.5.3
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 9.6 lists the register function in block
transfer mode.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once
the specified number of transfers has ended, a CPU interrupt is requested.
Table 9.6
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Rev.7.00 Mar. 18, 2009 page 442 of 1136
REJ09B0109-0700
SAR
or
DAR
Block Transfer Mode
Register Function in Block Transfer Mode
Figure 9.8 Memory Mapping in Block Transfer Mode
Nth block
First block
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Transfer
Block area
Function
Designates source address
Designates destination address
Holds block size
Designates block size count
Designates transfer count
DAR
or
SAR