HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 752

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 14 Watchdog Timer (WDT)
14.5
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 14.2 WDT Interrupt Source
Name
WOVI
14.6
14.6.1
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
Rev.7.00 Mar. 18, 2009 page 684 of 1136
REJ09B0109-0700
Legend:
WOVI: Interval timer interrupt request generation
H'FF
H'00
Interrupt Source
Usage Notes
Notes on Register Access
TCNT count
WT/IT=0
TME=1
Interrupt Source
TCNT overflow
Figure 14.3 Operation in Interval Timer Mode
Overflow
WOVI
Overflow
WOVI
Interrupt Flag
OVF
Overflow
WOVI
DTC Activation
Impossible
Overflow
WOVI
Time

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