HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 341

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface
DQMU, DQML
Precharge-sel
Address bus
SDRAMφ
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
Note: In the H8S/2373 Group, the synchronous DRAM interface is not supported.
Data bus
BREQO
BREQ
BACK
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
At least one state from sampling of BREQ signal.
RAS
CAS
CKE
φ
WE
External space read
NOP
T
1
[1]
T
2
[2]
PALL
[3]
address
NOP
Row
[4]
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[5]
Rev.7.00 Mar. 18, 2009 page 273 of 1136
[8]
Section 6 Bus Controller (BSC)
[6]
[7]
NOP
REJ09B0109-0700
[9]
CPU
cycle