HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 274

no-image

HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 6 Bus Controller (BSC)
Rev.7.00 Mar. 18, 2009 page 206 of 1136
REJ09B0109-0700
φ
Address bus
RASn (CSn)
UCAS, LCAS
RD
OE
Data bus
Note: n = 2 to 5
⎯ a refresh operation is initiated in the RAS down state
⎯ self-refreshing is performed
⎯ the chip enters software standby mode
⎯ the external bus is released
⎯ the RCDM bit or BE bit is cleared to 0
If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock
will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the
RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Figure 6.32 Example of Operation Timing in RAS Down Mode
T
Row address
p
DRAM space read
T
r
(RAST = 0, CAST = 0)
Column address 1
T
c1
T
c2
External address
Normal space
T
1
read
T
2
Column address 2
DRAM space
T
c1
read
T
c2

Related parts for HD6412373R