HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 295

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
6.7.10
Bus Cycle Control in Write Cycle
By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS
latency control cycle is disabled.
T
T
T
T
p
r
c1
c2
φ
SDRAMφ
Address bus
Column address
Row address
Column address
Precharge-sel
Row address
RAS
CAS
WE
CKE
High
DQMU, DQML
Data bus
PALL
ACTV
NOP
WRIT
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
(SDWCD = 1)
Rev.7.00 Mar. 18, 2009 page 227 of 1136
REJ09B0109-0700