HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 397

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the
DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at
this point, an interrupt request is sent to the CPU or DTC.
Figure 7.15 shows the operation flow in block transfer mode.
Figure 7.15 Operation Flow in Block Transfer Mode
MARB = MARB – DAIDE·(–1)
MARA = MARA – SAIDE·(–1)
MARB = MARB + DAIDE·(–1)
MARA = MARA + SAIDE·(–1)
Write to address specified by MARB
No
Read address specified by MARA
ETCRAL = ETCRAL – 1
ETCRB = ETCRB – 1
ETCRAL = ETCRAH
(DTE = DTME = 1)
Clear DTE bit to 0
Transfer request?
ETCRB = H'0000
ETCRAL = H'00
to end transfer
Release bus
Acquire bus
BLKDIR = 0
Start
Yes
Yes
Yes
Yes
SAID
DAID
Rev.7.00 Mar. 18, 2009 page 329 of 1136
·2
·2
DAID
SAID
DTSZ
DTSZ
·2
·2
·ETCRAH
·ETCRAH
DTSZ
DTSZ
Section 7 DMA Controller (DMAC)
No
No
No
REJ09B0109-0700

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