HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 493

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 9.1 shows a block diagram of the DTC.
9.1
• Transfer possible over any number of channels
• Three transfer modes
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space possible
• Activation by software is possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Module stop mode can be set
The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte),
enabling 32-bit/1-state reading and writing of the DTC register information.
DTCH803A_010020020400
⎯ Normal mode
⎯ Repeat mode
⎯ Block transfer mode
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
From 1 to 65,536 transfers can be specified.
One operation transfers one byte or one word of data.
Memory address is incremented or decremented by 1 or 2.
Once the specified number of transfers (1 to 256) has ended, the initial state is restored, and
transfer is repeated.
One operation transfers one block of data.
The block size is 1 to 256 bytes or words.
From 1 to 65,536 transfers can be specified.
Either the transfer source or the transfer destination is designated as a block area.
Features
Section 9 Data Transfer Controller (DTC)
Rev.7.00 Mar. 18, 2009 page 425 of 1136
Section 9 Data Transfer Controller (DTC)
REJ09B0109-0700