HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 848

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 I
16.3.4
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be
received.
Bit
7
6
5
Rev.7.00 Mar. 18, 2009 page 780 of 1136
REJ09B0109-0700
Bit Name
TIE
TEIE
RIE
I
2
C Bus Interrupt Enable Register (ICIER)
2
C Bus Interface 2 (IIC2) (Option)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit
enables or disables the transmit data empty
interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
Transmit End Interrupt Enable
This bit enables or disables the transmit end
interrupt (TEI) at the rising of the ninth clock while
the TDRE bit in ICSR is 1. TEI can be canceled by
clearing the TEND bit or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Receive interrupt enable
This bit enables or disables the receive data full
interrupt request (RXI) when a received data is
transferred from ICDRS to ICDRR and the RDRF
bit in ICSR is set to 1. RXI can be canceled by
clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) is
disabled.
1: Receive data full interrupt request (RXI) is
enabled.