HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 333

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Previous Access
Note:
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
Normal space write
DRAM/continuous
synchronous DRAM *
space write
* Not supported by the H8S/2378 Group.
Next Access
Normal space read
DRAM * /continuous
synchronous DRAM
space read
Normal space read
DRAM * /continuous
synchronous DRAM
space read
ICIS2
0
1
0
1
0
1
0
1
ICIS1
Rev.7.00 Mar. 18, 2009 page 265 of 1136
ICIS0
Section 6 Bus Controller (BSC)
DRMI
IDLC
0
1
0
1
0
1
0
1
REJ09B0109-0700
Idle cycle
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted
Disabled
1 state inserted
2 states inserted

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