HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 260

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
Table 6.5
Legend:
×: Don’t care.
6.6.3
If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data
Size and Data Alignment.
Rev.7.00 Mar. 18, 2009 page 192 of 1136
REJ09B0109-0700
Row
address
Column
address
MXC2 MXC1 MXC0
0
1
0
1
Data Bus
DRAMCR
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
×
×
×
0
1
×
×
×
0
1
0
1
10 bits A23
11 bits A23
8 bits
9 bits
Shift
Size
⎯
A23
A16
A23
A16
A23
A16
A16
A16
A23
A16
to
to
to
to
to
to
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Reserved (setting prohibited)
Reserved (setting prohibited)
Address Pins