HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 285

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all
bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT),
and mode-register write (MRS). Commands for bank control cannot be used.
6.7.2
With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Precharge-sel) can be output on
the upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0
and the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is
used.
Table 6.8
Legend:
×: Don’t care.
P: Precharge-sel
Row
address
Column
address
MXC2 MXC1 MXC0
Address Multiplexing
0
1
0
1
DRAMCR
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
×
×
0
1
0
1
×
×
0
1
0
1
0
1
0
1
Shift
8
bits
9
bits
10
bits
11
bits
Size A23 to
⎯
⎯
⎯
⎯
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Reserved (setting prohibited)
Reserved (setting prohibited)
P
P
P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Rev.7.00 Mar. 18, 2009 page 217 of 1136
P
P
Address Pins
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P
A8 A7 A6 A5 A4 A3 A2 A1 A0
Section 6 Bus Controller (BSC)
REJ09B0109-0700