HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 705

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
7
6
5
4
3
2
1
0
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
7
6
5
4
3
to
0
Bit
7
to
4
3
2
1
0
Bit Name
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Bit Name
NDR7
NDR6
NDR5
NDR4
Bit Name
NDR3
NDR2
NDR1
NDR0
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
All 1
Initial Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Description
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
1 is always read and write is disabled.
Description
Reserved
1 is always read and write is disabled.
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Section 12 Programmable Pulse Generator (PPG)
Rev.7.00 Mar. 18, 2009 page 637 of 1136
REJ09B0109-0700

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