HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 856

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 16 I
Rev.7.00 Mar. 18, 2009 page 788 of 1136
REJ09B0109-0700
(master output)
(master output)
(slave output)
(master output)
processing
(master output)
(slave output)
ICDRT
ICDRS
TDRE
TEND
User
processing
SDA
SDA
SCL
SCL
SDA
SDA
ICDRT
ICDRS
TDRE
TEND
User
[2] Instruction of start
2
condition issuance
[5] Write data to ICDRT. Clear TDRE.
C Bus Interface 2 (IIC2) (Option)
Figure 16.5 Master Transmit Mode Operation Timing 1
Figure 16.6 Master Transmit Mode Operation Timing 2
A
9
Bit 7
1
Bit 7
[3] Write data to ICDRT (first byte).
1
Bit 6
2
Clear TDRE.
Bit 6
Address + R/W
2
Bit 5
3
Address + R/W
Slave address
Bit 5
3
Bit 4
Data n
4
Data n
Bit 4
Bit 3
4
5
Bit 3
Bit 2
6
5
[4] Write data to ICDRT (second byte).
Bit 1
Clear TDRE and TEND.
Bit 2
7
6
[6] Issue stop condition. Clear TEND.
Bit 0
R/W
8
Bit 1
7
9
A
Bit 0
8
[7] Set slave receive mode
[5] Write data to ICDRT (third byte).
Clear TDRE.
A/A
9
Data 1
Data 1
Bit 7
1
Bit 6
Data 2
2

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