HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 346

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
6.14.4
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
6.14.5
Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the
synchronous DRAM interface. Do not change the DCTL pin during operation.
Connection Clock: Be sure to set the clock to be connected to the synchronous DRAM to
SDRAMφ.
WAIT Pin: In the continuous synchronous DRAM space, insertion of the wait state by the WAIT
pin is disabled regardless of the setting of the WAITE bit in BCR.
Bank Control: This LSI cannot carry out the bank control of the synchronous DRAM. All banks
are selected.
Burst Access: The burst read/burst write mode of the synchronous DRAM is not supported.
When setting the mode register of the synchronous DRAM, set to the burst read/single write and
set the burst length to 1.
CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit
to 0 in the DRAMCR.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Rev.7.00 Mar. 18, 2009 page 278 of 1136
REJ09B0109-0700
BREQO Output Timing
Notes on Usage of the Synchronous DRAM