HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 475

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR,
an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it
continues (as a burst) until the transfer end condition is satisfied.
If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Figures 8.31 to 8.34 show operation timing examples for various conditions.
φ pin
Bus cycle
CPU
operation
ETEND
EDA bit
φ pin
Bus cycle
CPU
operation
CPU cycle CPU cycle
CPU cycle CPU cycle
External
External
1
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Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode
Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode
External
External
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space
(CPU Cycles/Dual Address Mode/BGUP = 0)
(CPU Cycles/Dual Address Mode/BGUP = 1)
External
EXDMA
External
EXDMA
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read
read
EXDMA
EXDMA
write
write
1 bus cycle
CPU cycle
EXDMA
read
External
EXDMA
EXDMA
Rev.7.00 Mar. 18, 2009 page 407 of 1136
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write
read
Section 8 EXDMA Controller (EXDMAC)
Repeated
EXDMA
write
1 bus cycle
CPU cycle
Last transfer cycle
EXDMA
read
REJ09B0109-0700
EXDMA
EXDMA
write
read
CPU cycle
EXDMA
0
write