HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 473

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.4.11
Auto Request/Cycle Steal Mode/Normal Transfer Mode: When the EDA bit is set to 1 in
EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-
cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the
next transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 8.28 to 8.30 show operation timing examples for various conditions.
φ pin
Bus cycle
CPU
operation
ETEND
EDA bit
Examples of Operation Timing in Each Mode
EDA = 1
write
Figure 8.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
0
Bus release
1
Internal bus space
3 cycles
cycles
(No Contention/Dual Address Mode)
EXDMA
read
EXDMA
write
1 cycle
Bus
release
EXDMA
Rev.7.00 Mar. 18, 2009 page 405 of 1136
read
Section 8 EXDMA Controller (EXDMAC)
EXDMA
write
Bus
release
EXDMA
Last transfer cycle
read
REJ09B0109-0700
EXDMA
write
0