HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 292

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
6.7.8
When the command interval specification from the ACTV command to the next READ/WRIT
command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted
between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column
address by setting the RCD1 and RCD0 bits of DRACCR. Use the optimum setting for the wait
time according to the synchronous DRAM connected and the operating frequency of this LSI.
Figure 6.46 shows an example of the timing when the one Trw state is set.
Rev.7.00 Mar. 18, 2009 page 224 of 1136
REJ09B0109-0700
Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State
Row Address Output State Control
Read
Write
Address bus
DQMU, DQML
DQMU, DQML
Precharge-sel
Data bus
Data bus
SDRAMφ
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)
CKE
CKE
RAS
RAS
CAS
CAS
WE
WE
φ
Column
address
PALL
PALL
T
p
ACTV
ACTV
T
r
Row address
Row address
NOP
High
High
T
rw
NOP
READ
T
c1
Column address
WRIT
T
cl
NOP
NOP
T
c2