HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 321

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in
BCR are valid. However, in the case of consecutive reads in different areas, for example, if the
second read is a full access to DRAM space, only a T
timing in this case is shown in figure 6.69.
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.70 and 6.71.
Figure 6.69 Example of DRAM Full Access after External Read
Address bus
Data bus
RD
φ
T
1
External read
T
2
(CAST = 0)
T
3
p
T
p
cycle is inserted, and a T
Rev.7.00 Mar. 18, 2009 page 253 of 1136
DRAM space read
T
r
T
Section 6 Bus Controller (BSC)
c1
T
c2
i
REJ09B0109-0700
cycle is not. The