MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 151

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.8 SIM Registers
MC68HC908LJ12
Freescale Semiconductor
INT/BREAK
ICLK
IAB
NOTE:
—
Figure 9-19. Stop Mode Recovery from Interrupt or Break
Rev. 2.1
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
The SIM has three memory-mapped registers:
•
•
•
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
STOP +1
SIM Break Status Register (SBSR) — $FE00
SIM Reset Status Register (SRSR) — $FE01
SIM Break Flag Control Register (SBFCR) — $FE03
R/W
IDB
IAB
instruction.
System Integration Module (SIM)
STOP ADDR
Figure 9-18. Stop Mode Entry Timing
Figure 9-18
STOP + 2
PREVIOUS DATA
STOP RECOVERY PERIOD
STOP + 2
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SP
System Integration Module (SIM)
SP – 1
SAME
SAME
SP – 2
SAME
Technical Data
SP – 3
SAME
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