MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 381

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.4.4 LVI Trip Selection
21.5 LVI Status Register
MC68HC908LJ12
Freescale Semiconductor
NOTE:
—
Rev. 2.1
Address:
Reset:
The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select
whether the LVI is configured for 5V or 3.3 V operation. (See
Configuration Registers
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V
Section 23. Electrical Specifications
The LVI status register (LVISR) controls LVI interrupt functions and
indicates if the V
LVIOUT — LVI Output Bit
Read: LVIOUT
Write:
This read-only flag becomes set when the V
V
TRIPF
$FE0F
Bit 7
TRIPF
0
trip voltage (see
[5 V] or V
Table 21-1. LVI Status Register (LVISR)
Low-Voltage Inhibit (LVI)
= Unimplemented
V
LVIIE
TRIPF
DD
6
0
Table 21-2. LVIOUT Bit Indication
V
V
voltage was detected below the V
DD
DD
< V
V
> V
< V
TRIPF
LVIIF
DD
DD
5
0
TRIPR
TRIPF
(CONFIG).)
< V
Table
[3.3 V]) may be lower than this. (See
TRIPR
LVIIAK
21-2). Reset clears the LVIOUT bit.
4
0
0
for the actual trip point voltages.)
Previous value
3
0
0
LVIOUT
DD
0
1
voltage falls below the
2
0
0
Low-Voltage Inhibit (LVI)
TRIPF
1
0
0
Technical Data
level.
Section 5.
Bit 0
0
0
381