MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 310

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Analog-to-Digital Converter (ADC)
15.8 I/O Registers
15.8.1 ADC Status and Control Register
Technical Data
310
Address:
These I/O registers control and monitor operation of the ADC:
This section describes the function of the ADC status and control
register (ADSCR). Writing ADSCR aborts the current conversion and
initiates a new conversion.
COCO — Conversions Complete Bit
AIEN — ADC Interrupt Enable Bit
Reset:
Read:
Write:
•
•
•
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADSCR is written, or whenever the ADC clock control register is
written, or whenever the ADC data register low, ADRL, is read.
If the AIEN bit is logic 1, the COCO bit always read as logic 0, CPU to
service the ADC interrupt will be generated at the end if an ADC
conversion. Reset clears the COCO bit.
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register,
ADR0, is read or the ADSCR is written. Reset clears the AIEN bit.
Figure 15-4. ADC Status and Control Register (ADSCR)
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN=1)
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADC status and control register, ADSCR
ADC data register, ADRH:ADRL
ADC clock register, ADCLK
$003C
COCO
Analog-to-Digital Converter (ADC)
0
= Unimplemented
AIEN
0
ADCO
0
ADCH4
1
ADCH3
1
MC68HC908LJ12
ADCH2
Freescale Semiconductor
1
ADCH1
1
—
Rev. 2.1
ADCH0
1