MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 305

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.4.2 Voltage Conversion
15.4.3 Conversion Time
MC68HC908LJ12
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 2.1
When the input voltage to the ADC equals V
signal to $3FF (full scale). If the input voltage equals V
converts it to $000. Input voltages between V
straight-line linear conversions. All other input voltages will result in
$3FF if greater than V
Input voltage should not exceed the analog supply voltages.
Conversion starts after a write to the ADSCR. A conversion is between
16 and 17 ADC clock cycles, therefore:
The ADC conversion time is determined by the clock source chosen and
the divide ratio selected. The clock source is either the bus clock or
CGMXCLK and is selectable by the ADICLK bit located in the ADC clock
register. The divide ratio is selected by the ADIV[2:0] bits.
For example, if a 4MHz CGMXCLK is selected as the ADC input clock
source, with a divide-by-2 prescale, and the bus speed is set at 8MHz:
The ADC frequency must be between f
maximum to meet ADC specifications. See
Characteristics.
Since an ADC cycle may be comprised of several bus cycles (eight in the
previous example) and the start of a conversion is initiated by a bus cycle
write to the ADSCR, from zero to four additional bus cycles may occur
before the start of the initial ADC cycle. This results in a fractional ADC
cycle and is represented as the 17th cycle.
Number of bus cycles = conversion time × bus frequency
Number of bus cycles = 8µs x 8MHz = 64 to 68 cycles
Analog-to-Digital Converter (ADC)
Conversion time =
Conversion time =
REFH
and $000 if less than V
16 to 17 ADC cycles
16 to17 ADC cycles
ADC frequency
4MHz ÷ 2
ADIC
Analog-to-Digital Converter (ADC)
REFH
23.6 5.0V DC Electrical
minimum and f
REFH
, the ADC converts the
REFL
and V
= 8 to 8.5 µs
REFL
.
REFL
ADIC
Technical Data
, the ADC
are
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