MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 29

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LJ12
Freescale Semiconductor
Technical Data — MC68HC908LJ12
—
Rev. 2.1
Table
2-1
5-1
6-1
6-2
8-1
8-3
8-2
9-1
9-2
9-3
10-1 Monitor Mode Signal Requirements and Options . . . . . . . . . . 160
10-2 Mode Differences (Vectors) . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10-3 Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 164
10-4 READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 165
10-5 WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 166
10-6 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 166
10-7 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 167
10-8 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 167
10-9 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 168
10-10 Summary of ROM-Resident Routines . . . . . . . . . . . . . . . . . . 171
10-11 PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10-12 ERARNGE Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
10-13 LDRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
10-14 MON_PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
10-15 MON_ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
LVI Trip Point Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Numeric Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . .120
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . . 120
List of Tables
Title
List of Tables
Technical Data
Page
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