MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 287

IC MCU 12K FLASH 4/8MHZ 64-QFP

MC908LJ12CFUE

Manufacturer Part Number
MC908LJ12CFUE
Description
IC MCU 12K FLASH 4/8MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ12CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ12CFUE
Manufacturer:
FREESCALE
Quantity:
4 330
Part Number:
MC908LJ12CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908LJ12CFUE
Manufacturer:
FREESCALE
Quantity:
4 330
Part Number:
MC908LJ12CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908LJ12
Freescale Semiconductor
Rev. 2.1
Reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. The clearing mechanism
for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, regardless of the state of the
SPE bit. (See
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.
ERRIE
MODF
OVRF
R
Serial Peripheral Interface Module (SPI)
Figure 14-11. SPI Interrupt Request Generation
Figure
14-11.)
SPRIE
SPTE
SPTIE
SPRF
SPE
Serial Peripheral Interface Module (SPI)
NOT AVAILABLE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
NOT AVAILABLE
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Technical Data
287

Related parts for MC908LJ12CFUE