MC908LJ12CFUE Freescale Semiconductor, MC908LJ12CFUE Datasheet - Page 75

• Manufacturer Part Number: MC908LJ12CFUE
• Description: IC MCU 12K FLASH 4/8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.5 Configuration Register 2 (CONFIG2)
MC68HC908LJ12
Freescale Semiconductor
—
Rev. 2.1
Address:
STOP_IRCDIS — Internal RC Oscillator Stop Mode Disable
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
DIV2CLK — Divide-by-2 Clock Bypass
Reset:
Read:
Write:
Setting STOP_IRCDIS disables the internal RC oscillator during stop
mode. When this bit is cleared, the internal RC oscillator continues to
operate in stop mode. Reset clears this bit.
Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator
to continue operating during stop mode. This is useful for driving the
real time clock module to allow it to generate periodic wake-up while
in stop mode. When this bit is cleared, the external XTAL oscillator will
be disabled during stop mode. Reset clears this bit.
When CGMXCLK is selected to drive the system clocks (BCS=0),
setting DIV2CLK allows the CGMXCLK to bypass the divide-by-2
divider in the CGM module; CGMOUT will equal CGMXCLK and bus
clock will equal CGMXCLK divide-by-2.
DIV2CLK bit has no effect when the BCS=1 in the PLL control
register (CGMVCLK selected and divide-by-2 always enabled). Reset
clears this bit.
1 = Internal RC oscillator disabled during stop mode
0 = Internal RC oscillator enabled during stop mode
1 = XTAL oscillator enabled during stop mode
0 = XTAL oscillator disabled during stop mode
1 = Divide-by-2 divider bypassed;
0 = Divide-by-2 divider enabled;
$001D
Bit 7
Figure 5-3. Configuration Register 2 (CONFIG2)
Configuration Registers (CONFIG)
When BSC=0, CGMOUT equals CGMXCLK
When BSC=0, CGMOUT equals CGMXCLK divide-by-2
0
0
= Unimplemented
IRCDIS
STOP_
6
0
XCLKEN
STOP_
5
0
DIV2CLK
4
0
†† Reset by POR only.
PCEH
3
0
Configuration Registers (CONFIG)
PCEL
2
0
LVISEL1
0
1
††
Technical Data
LVISEL0
Bit 0
0
††
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